The goal of this project was to build an efficient low level implementation of the Boids Algorithm - an algorithm that simulates the flocking behavior of birds, or organisms in general.

The initial simulation was done in Python, where we showed the limitations we get when we try to simulate a large number of boids on a CPU-like architecture. We decided to create a hardware level implementation of this algorithm using Verilog and FPGAs to demonstrate that a much more efficient computational model is possible at the hardware level.

A detailed writeup can be found on the github readme, but the general outline of the project can be seen below:

• » High Level Simulations
  •         » Python Pygame Simulation (with no use of multiplication/division)
  •         » Simulation in C (with a few optimizations)
• » Compilation
•         » Custom compilation from C to our custom MIPS instruction set
•         » Custom MIPS simulator (test our compiled code, before time intensive FPGA testing)
•         » Testing for our CPU with a verilog testbench
• » Custom Hardware Units (Verilog)
•         » BPU (Boid Processing Unit, deals with a single boid's information)
•         » Canvas RAM (Custom RAM implementation that allows for extremely VGA Screen updates)
•         » VGA Screen Controller (Controls interactions with display)
•         » I/O & regfile (custom implentation for better communication)
• » CPU
•         » Custom built 5-stage pipelined MIPS CPU
•         » Has its own seperate section here
• » Future Work/Bloopers
•         » More details about the project and work can be found on the GitHub